Title page for ETD etd-01312008-113612

Type of Document Master's Thesis
Author Newcomb, Jamie David
Author's Email Address jdnewcom@vt.edu
URN etd-01312008-113612
Title A Scalable Approach to Multi-core Prototyping
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Patterson, Cameron D. Committee Chair
Buehrer, Richard Michael Committee Member
Schaumont, Patrick Robert Committee Member
  • multi-gigabit
  • Aurora
  • Xilinx
  • FPGA
  • multi-processor array
  • multi-core
Date of Defense 2008-01-25
Availability unrestricted
In recent years, multi-core processors and multi-processor networks have grown in popularity as a solution to the limits on increasing clock speed, rising power consumption, and the nanometer manufacturing processes. Multi-core processors and multi-processor networks are seen as the next step in the advancement of computational capabilities by way of concurrent processing. However, parallel software design is difficult due to the immaturity of scalable architectures and software development environments for multi-core hardware.

How should processors effectively and quickly pass information, with as little overhead as possible? What kind of communication architecture is best suited for parallelism? How can large-scale architectures be quickly produced, verified and properly utilized by software? Using commercially available FPGA development boards, Xilinx tools and components, this thesis offers a light-weight solution to these questions for effective, low-overhead, low-latency multi-core communication and fast prototyping of multi-processor networks for scalable processor arrays.

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