Title page for ETD etd-01312009-063336

Type of Document Master's Thesis
Author Gowrisankaran, Prabhakar
URN etd-01312009-063336
Title Structural testbench development for DSP models
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Armstrong, James R. Committee Chair
Athanas, Peter M. Committee Member
Gray, Festus Gail Committee Member
  • test bench development
Date of Defense 1995-03-05
Availability restricted

Generation of test benches for large DSP behavioral models is a complicated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the modeler of the details of test bench development. Two approaches being explored are: 1) behavioral - the CASE tools develop complete high level models of the test bench, and 2) structural- a library of primitive components is developed so that a conventional schematic capture tool, e.g., Synopsys Graphical Environment, can be used to construct the test bench. An intelligent interface prompts the user for high level test bench information, and inserts this information into the test bench code. The intelligent interface also allows the user to specify and control file I/O as a data source.

The objective of this thesis is the development of a set of library models from which a structural test bench can be created. This thesis also describes creation of the structural test bench using the library of primitive components and Synopsys Graphical Environment, a conventional schematic capture tool. This approach has been implemented for two applications: 1) A 2D Image processing algorithm - InfraRed Search and Track (IRST) and 2) Synthetic Aperture Radar (SAR). An intelligent interface developed in C combines the structural model with user information which provides for generics and inputs. This thesis also shows how a requirements capture tool can be used to generate generic values.

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