Title page for ETD etd-02062003-145930

Type of Document Master's Thesis
Author Jayaram, Vinay B.
Author's Email Address vbj@vt.edu
URN etd-02062003-145930
Title Experimental Study of Scan Based Transition Fault Testing Techniques
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Hsiao, Michael S. Committee Chair
Baker, James M. Jr. Committee Member
Shukla, Sandeep K. Committee Member
  • broad-side
  • ATPG
  • test coverage
  • skewed load
  • transition faults
  • pattern volume
Date of Defense 2003-01-29
Availability unrestricted
The presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and Skewed load delay test (Launch-from-shift). Each method has its own drawbacks and many practical issues are associated with pattern generation and application. Our work focuses on the implementation and comparison of these transition fault testing techniques on multiple industrial ASIC designs. In this thesis, we present results from multiple designs and compare the two techniques with respect to test coverage, pattern volume and pattern generation time. For both methods, we discuss the effects of multiple clock domains, tester hardware considerations, false and multi-cycle paths and the implications of using a low cost tester. We then consider the implications of pattern volume on testing both stuck-at and transition faults and the effects of using transition fault patterns to test stuck-at faults. Finally, we present results from our analysis on switching activity of nets in the design, while executing transition fault patterns.
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