Title page for ETD etd-02242009-162329

Type of Document Dissertation
Author Tolentino, Matthew Edward
URN etd-02242009-162329
Title Managing Memory for Power, Performance, and Thermal Efficiency
Degree PhD
Department Computer Science
Advisory Committee
Advisor Name Title
Cameron, Kirk W. Committee Chair
Beihl, Gary M. Committee Member
Butt, Ali R. A. Committee Member
Nikolopoulos, Dimitrios S. Committee Member
Ribbens, Calvin J. Committee Member
  • Energy Efficiency
  • Control Theory
  • Memory Management
  • Operating Systems
Date of Defense 2009-02-18
Availability unrestricted
Extraordinary improvements in computing performance, density, and capacity have driven rapid increases in system energy consumption, motivating the need for energy-efficient performance. Harnessing the collective computational capacity of thousands of these systems can consume megawatts of electrical power, even though many systems may be underutilized for extended periods of time. At scale, powering and cooling unused or lightly loaded systems can waste millions of dollars annually.

To combat this inefficiency, we propose system software, control systems, and architectural techniques to improve the energy efficiency of high-capacity memory systems while preserving performance. We introduce and discuss several new application-transparent, memory management algorithms as well as a formal analytical model of a power-state control system rooted in classical control theory we developed to proportionally scale memory capacity with application demand. We present a prototype implementation of this control-theoretic runtime system that we evaluate on sequential memory systems. We also present and discuss why the traditional performance-motivated approach of maximizing interleaving within memory systems is problematic and should be revisited in terms of power and thermal efficiency. We then present power-aware control techniques for improving the energy efficiency of symmetrically interleaved memory systems. Given the limitations of traditional interleaved memory configurations, we propose and evaluate unorthodox, asymmetrically interleaved memory configurations. We show that when coupled with our control techniques, significant energy savings can be achieved without sacrificing application performance or memory bandwidth.

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