Title page for ETD etd-031099-213422

Type of Document Master's Thesis
Author Hameed, Qaisar
Author's Email Address qhameed@ee.vt.edu
URN etd-031099-213422
Title A Behavioral Test Strategy For Board Level Systems
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Gray, Festus Gail Committee Chair
Armstrong, James R. Committee Member
Ha, Dong Sam Committee Member
  • March X
  • Smart Model
  • Start Small
  • VHDL
  • Assembly
  • Legacy Systems
  • Testing
Date of Defense 1999-03-03
Availability unrestricted
A digital board typically contains a heterogeneous

mixture of chips: microprocessors, memory,

control and I/O logic. Different testing

techniques are needed for each of these

components. To test the whole board, these

techniques must be integrated into an overall

testing strategy for the board. In this thesis,

we have applied a behavioral testing scheme to

test the board. Each component chip is tested by

observing the behavior of the system in response

to the test code, i.e. the component under test

is not isolated from the rest of the circuit

during test. This obviates the need for the

extra hardware used for isolating the chips that

is required for structural testing. But this is

done at the cost of reduced fault location,

although fault detection is still adequate.

We have applied the start small approach to

behavioral testing. We start by testing a small

core of functions. Then, only those functions

already tested are used to test the remaining

behavior. The grand goal is testing the whole

board. This is divided into goals for testing

each of the individual chips, which is further

subdivided into sub-goals for each of the

sub-functions of the board or sub-goals for

testing for the most common faults in a

component. Each component is tested one by one.

Once a component passes, it is put in a passed

items set and then can be used in testing the

remaining components. Using the start small

approach helps isolate the faults to the chip

level and thus results in better fault location

than the simple behavioral testing scheme in

which there is no concept of passed items set and

its usage. As an example, this testing approach

is applied to a microcontroller based temperature

sensor board. This code is run on the VHDL model

of the system, and then also on the actual

system. For modeling the system in VHDL, Synopsys

Smart model library components are used. Faults

are injected in the system and then the

performance of the strategy is evaluated. This

strategy is found to be very effective in

detecting internal faults of the chip and

locating the faults to the chip level. The

interconnection faults are difficult to locate

although they are detected in most of the cases.

Different scenarios for incorporating this scheme

in legacy systems are also discussed.

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  appendix.pdf 196.96 Kb 00:00:54 00:00:28 00:00:24 00:00:12 00:00:01
  chap2.pdf 2.83 Mb 00:13:06 00:06:44 00:05:54 00:02:57 00:00:15
  chap3.pdf 275.07 Kb 00:01:16 00:00:39 00:00:34 00:00:17 00:00:01
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  chap5nref.pdf 16.06 Kb 00:00:04 00:00:02 00:00:02 00:00:01 < 00:00:01
  introchap1.pdf 63.46 Kb 00:00:17 00:00:09 00:00:07 00:00:03 < 00:00:01
  vita.pdf 2.82 Kb < 00:00:01 < 00:00:01 < 00:00:01 < 00:00:01 < 00:00:01

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