Title page for ETD etd-04302004-104254

Type of Document Master's Thesis
Author Lewis, Jr., Charles William
Author's Email Address chjr2@vt.edu
URN etd-04302004-104254
Title Support for Send-and-Receive Based Message-Passing for the Single-Chip Message-Passing Architecture
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Baker, James M. Jr. Committee Chair
Arthur, James D. Committee Member
Jones, Mark T. Committee Member
  • Single-Chip Computer
  • Parallel Computing
  • Message-Passing
Date of Defense 2004-04-28
Availability unrestricted

Arguably, from the programmer's perspective, the programming model is the most important characteristic of any computer system. Perhaps this explains why, after many decades of research, architects and programmers alike continue to debate the appropriate programming model for parallel computers. Though thousands of programming models have been developed, standards such as PVM and MPI have made send-and-receive based message-passing the most popular programming model for distributed memory architectures. This thesis explores modifying the Single-Chip Message-Passing (SCMP) architecture to more efficiently support send-and-receive based message-passing. The proposed system is compared, for performance and programmability, to the active messaging programming model currently used by SCMP.

SCMP offers a unique platform for send-and-receive based message-passing. The SCMP design incorporates multiple multi-threaded processors, memory, and a network onto a single chip. This integration reduces the penalties of thread switching, memory access, and inter-process communication typically seen on more traditional distributed memory parallel machines. The mechanisms proposed in this thesis to support send-and-receive based message-passing on SCMP attempt to preserve and exploit these features as much as possible.

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