Title page for ETD etd-05022009-040753
|Type of Document
||Process level test generation for VHDL behavioral models
||Master of Science
|Armstrong, James R.
|Cyre, Walling R.
|Gray, Festus Gail
|Date of Defense
This thesis describes the development of the Process Test Generation (PTG) software for
the testing of single-process VHDL behavioral models. The PTG software, along with
Hierarchical Behavioral Test Generator (HBTG) and Modeler's Assistant, forms a part of
the Automatic Test Generation System being developed at Virginia Tech. The PTG
software transforms the VHDL description of a circuit, given by Modeler's Assistant, into
a Control Flow Graph (CFG) that describes the control and data flow information in the
behavioral model. The process test generation algorithm, called the PTG algorithm, uses
the CFG to generate stimulus/response test sets that test all the functions of the VHDL
model. The algorithm creates events on signals, propagates these events and uses
simulation to obtain responses. Various features present in the software like the
generation of the Control Flow Graph, the PTG algorithm, and the construction of paths
through the CFG to propagate and justify events, are discussed. The test sets generated
by PTG can be used for the hierarchical test generation by HBTG, which was developed
earlier. Another program, called Test Bench Generator (TBG), is presented in this thesis.
It is used to convert the test sequence generated by HBTG into a VHDL Test Bench that
can be used for simulation.
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