Title page for ETD etd-05032004-114851

Type of Document Master's Thesis
Author Nguyen, Huy
Author's Email Address hunguye6@vt.edu, dinguye4@hotmail.com
URN etd-05032004-114851
Title Design, Analysis and Implementation of Multiphase Synchronous Buck DC-DC Converter for Transportable Processor
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Lai, Jason Committee Chair
Boroyevich, Dushan Committee Member
Huang, Alex Q. Committee Member
  • Multiphase Synchronous Buck
  • VRC
  • Laptop Processor
  • Load Line
Date of Defense 2004-04-26
Availability unrestricted
As laptop mobile users expect more application features and long battery life, the processor current has to increase to response the demanding while the voltage has to decease to save the power loss. Therefore, it is necessary for a system designer to improve the efficiency of the voltage regulator converter (VRC) for the processor. Laptop processor architecture is more complicated than desktop because of different mode operations and their transitions. The laptop processor runs at different voltage levels for each operation mode to save the battery life. Therefore, the VRC needs to supply the correct and stable voltage to the processor. In this thesis, an analysis of power loss is derived to estimate the efficiency and switching frequency, three widely current sensing methods are discussed, two methods to compensate for the thermal resistance in loss less current sense methods are proposed, the tolerance of load line base on the component’s tolerance in the converter is analyzed, the equation to estimate the output capacitance is derived, and the small signal analysis of multiphase synchronous buck converter with the droop current loop is derived.

A hardware prototype was implemented base on 4-phase synchronous buck topology to provide high efficiency and lower cost solution. The results of load line meets the Intel specification in different modes of operation, provides the best transient responses, and meets the specification during the load transient. The control loop lab measurement is also matched with the analysis and simulation.

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