Title page for ETD etd-05042007-092729

Type of Document Master's Thesis
Author Simpson, Eric
Author's Email Address esimpson@vt.edu
URN etd-05042007-092729
Title Runtime Intellectual Property Protection on Programmable Platforms
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Schaumont, Patrick Robert Committee Chair
Ha, Dong Sam Committee Member
Shukla, Sandeep K. Committee Member
  • runtime protection
  • intellectual property
  • HW/SW authentication
  • PUF
  • IP
  • programmable platform
  • FPGA
Date of Defense 2007-04-30
Availability unrestricted
Modern Field-Programmable Gate Arrays (FPGAs) can accommodate complex

system-on-chip designs and require extensive intellectual-property (IP)

support. However, current IP protection mechanisms in FPGAs are limited, and

do not reach beyond whole-design bitstream encryption. This work presents

an architecture and protocol for securing IP based designs in programmable

platforms. The architecture is reprsented by the Secure Authentication Module

(SAM), an enabler for next-generation intellectual-property exchange in

complex FPGAs. SAM protects hardware, software, application data, and also

provides mutual assurances for the end-user and the intellectual-property

developer. Further, this work demonstrates the use of SAM in a secure video

messaging device on top of a Virtex-II Pro development system

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