Title page for ETD etd-05192010-020151

Type of Document Dissertation
Author Ahuja, Sumit
Author's Email Address sahuja@vt.edu
URN etd-05192010-020151
Title High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Shukla, Sandeep K. Committee Chair
Abbott, A. Lynn Committee Member
Hsiao, Michael S. Committee Member
Schaumont, Patrick Robert Committee Member
Vullikanti, Anil Kumar S. Committee Member
  • High Level Synthesis
  • Model Checking
  • Power Estimation
  • Clock-gating
  • Power Reduction
  • Coprocessors.
  • Hardware Software Co-design
  • Electronic System Level
Date of Defense 2010-05-12
Availability unrestricted
The unabated continuation of the Moore’s law has allowed the doubling of the number of transistors

per unit area of a silicon die every 2 years or so. At the same time, an increasing demand on

consumer electronics and computing equipments to run sophisticated applications has led to an

unprecedented complexity of hardware designs. These factors have necessitated the abstraction

level of design-entry of hardware systems to be raised beyond the Register-Transfer-Level (RTL)

to Electronic System Level (ESL). However, power envelope on the designs due to packaging and

other thermal limitations, and the energy envelope due to battery life-time considerations have also created a need for power/energy efficient design. The confluence of these two technological issues has created an urgent need for solving two problems: (i) How do we enable a power-aware design flow with a design entry point at the Electronic System Level? (ii) How do we enable power aware High Level Synthesis to automatically synthesize RTL implementation from ESL?

This dissertation distinguishes itself by addressing the following two issues: (i) Since power/energy consumption of electronic systems largely depends on implementation details, and high-level models abstract away from such details, power/energy estimation at such levels has not been addressed thoroughly. (ii) A lot of work has been done in applying various techniques on control-data-flow graphs (CDFG) to find power/area/latency pareto points during behavioral synthesis. However, high level C-based functional models of various compute-intensive components, which could be easily synthesized as co-processors, have many opportunities to reduce power. Some of these savings opportunities are traditional such as clock-gating, operand-isolation etc. The exploration of alternate granularities of these techniques with target applications in mind, opens the door for

traditional power reduction opportunities at the high-level.

This work therefore concentrates on the aforementioned two areas of inadequacy of hardware design methodologies. Our proposed solutions include utilizing ESL simulation traces and mapping those to lower abstraction levels for power estimation, derivation of statistical power models using regression based learning for power estimation at early design stages, etc. On the HLS front, techniques that insert the power saving features during the synthesis process using exploration of granularity and scope of clock-gating, sequential clock-gating are proposed. Finally, this work shows how to marry two domains, that is estimation and reduction. In this regard, a power model is proposed, which helps in predicting power savings obtained using clock-gating and further guiding HLS to selectively insert clock-gating.

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