Title page for ETD etd-06102012-040521

Type of Document Master's Thesis
Author Lee, Hyung Ki
URN etd-06102012-040521
Title On detection of stuck-open faults using stuck-at test sets in CMOS combinational circuits
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Ha, Dong Sam Committee Chair
Midkiff, Scott F. Committee Member
Tront, Joseph G. Committee Member
  • Complementary
  • Metal oxide semiconductors
Date of Defense 1989-03-15
Availability restricted

The traditional line stuck-at fault model does not properly represent transistor stuck-open (SOP) faults in complementary metal oxide semiconductor (CMOS) circuits. In general, test generation methods for detecting CMOS SOP faults are complex and time consuming due to the sequential behavior of faulty circuits. The majority of integrated circuit manufacturers still rely on stuck-at test sets to test CMOS combinational circuits at the risk of some SOP faults not being detected.

In this thesis we investigate two aspects regarding the detection of SOP faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequences of stuck-at test sets. The performance of the proposed method is compared with those of competing methods. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage.

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