Title page for ETD etd-06122012-134840

Type of Document Master's Thesis
Author Lindsay, Aaron Charles
Author's Email Address aaron.lindsay@vt.edu
URN etd-06122012-134840
Title LWFG: A Cache-Aware Multi-core Real-Time Scheduling Algorithm
Degree Master of Science
Department Computer Science
Advisory Committee
Advisor Name Title
Kafura, Dennis G. Committee Co-Chair
Ravindran, Binoy Committee Co-Chair
Vullikanti, Anil Kumar S. Committee Member
  • Linux
  • Real-Time
  • Scheduling
  • Multiprocessors
  • Cache-aware
  • Partitioning
Date of Defense 2012-06-08
Availability unrestricted
As the number of processing cores contained in modern processors continues to increase, cache hierarchies are becoming more complex. This added complexity has the effect of increasing the potential cost of any cache misses on such architectures. When cache misses become more costly, minimizing them becomes even more important, particularly in terms of scalability concerns.

In this thesis, we consider the problem of cache-aware real-time scheduling on multiprocessor systems. One avenue for improving real-time performance on multi-core platforms is task partitioning. Partitioning schemes statically assign tasks to cores, eliminating task migrations and reducing system overheads. Unfortunately, no current partitioning schemes explicitly consider cache effects when partitioning tasks.

We develop the LWFG (Largest Working set size First, Grouping) cache-aware partitioning algorithm, which seeks to schedule tasks which share memory with one another in such a way as to minimize the total number of cache misses. LWFG minimizes cache misses by partitioning tasks that share memory onto the same core and by distributing the system's sum working set size as evenly as possible across the available cores.

We evaluate the LWFG partitioning algorithm against several other commonly-used partitioning heuristics on a modern 48-core platform running ChronOS Linux. Our evaluation shows that in some cases, the LWFG partitioning algorithm increases execution efficiency by as much as 15% (measured by instructions per cycle) and decreases mean maximum tardiness by up to 60%.

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