Title page for ETD etd-06222010-020057

Type of Document Master's Thesis
Author Burnette, David G
URN etd-06222010-020057
Title A graphical representation for VHDL models
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Armstrong, James R. Committee Chair
Ha, Dong Sam Committee Member
Tront, Joseph G. Committee Member
  • Electronic circuits
Date of Defense 1988-05-14
Availability restricted
This paper describes a graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the Modified Process Model Graph, adds several new constructs to handle more features of VHDL. These new constructs include: variables inside process blocks, a visual notation for sensitivity lists, and a clear visual indication of the interface to an object. A software tool, called VHDLCad* (c)* * , has been developed that uses produces VHDL source code interactively from the graphical representation. The tool allows the user to use pre-defined modules, or create new modules and place them in the library. With the benefit of a graphical representation, a menu-driven system and re-usable code, VHDLCad can improve the productivity of VHDL modelers.

*VHDLCad is a trademark of David G. Burnette.

**Copyright 1988 by David G. Burnette. All rights reserved

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