Title page for ETD etd-07012009-203400

Type of Document Master's Thesis
Author Carrick, Matthew
Author's Email Address mcarrick@vt.edu
URN etd-07012009-203400
Title Logical Representation of FPGAs and FPGA Circuits within the SCA
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Dietrich, Carl B. Committee Chair
Athanas, Peter M. Committee Member
Reed, Jeffrey Hugh Committee Member
  • FPGA
  • Software Radio
  • SCA
Date of Defense 2009-07-02
Availability unrestricted
A very basic engineering tradeoff is performance versus flexibility and this design choice must be made when developing a software radio. Hardware devices such as General Purpose Processors (GPPs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) all provide a designer with choices along the performance versus flexibility spectrum. The designer must choose a combination of GPP, DSP, FPGA and ASIC devices to balance the needs of performance versus flexibility.

The Software Communications Architecture (SCA) is a specification for a software radio architecture produced by the Joint Program Executive Office (JPEO) Joint Tactical Radio System (JTRS). The 2.2 revision of the SCA only implies support for GPPs, with no specified support for additional devices such as FPGAs. However, FPGA integration within the scope of the SCA is still possible.

The integration of an additional processing hardware device other than a GPP requires the ability to logically represent the device within the Core Framework. This representation is implemented within the OSSIE Core Framework, an open source implementation of the SCA. The representation requires the support of multiple implementations of signal processing components within the framework, a simple component deployment model, and the abstraction of the FPGA interactions into a software component.

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