Title page for ETD etd-07072011-145912

Type of Document Master's Thesis
Author Tavaragiri, Abhay
Author's Email Address abhay@vt.edu
URN etd-07072011-145912
Title A Management Paradigm for FPGA Design Flow Acceleration
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Schaumont, Patrick Robert Committee Member
Tront, Joseph G. Committee Member
  • FPGA Management Technique
  • XML
  • Productivity
  • TORC
Date of Defense 2011-07-07
Availability unrestricted
Advances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental productivity flow, focusing on the back-end FPGA design is provided in this thesis. This thesis presents a management paradigm that is used to capture the design specific information in a format that is reusable across the entire design process. A C++ based internal data structure stores all the information, whereas XML is used to provide an external view of the design data. This work provides a vendor independent, universal format for representing the logical and physical information associated with FPGA designs.
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