Title page for ETD etd-07262010-184604

Type of Document Master's Thesis
Author Lakshmanan, Karthick
Author's Email Address karthickl@vt.edu
URN etd-07262010-184604
Title Design of an Automation Framework for a Novel Data-Flow Processor Architecture
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Jones, Mark T. Committee Chair
Martin, Thomas L. Committee Co-Chair
Plassmann, Paul E. Committee Member
  • Electronic Textiles
  • Automation Framework
  • Data-Flow
Date of Defense 2010-07-21
Availability unrestricted
Improved process technology has resulted in the integration of computing elements into multiple application areas. General purpose micro-controllers are designed to assist in this integration through a flexible design. The application areas, however, are so diverse in nature that the general purpose micro-controllers may not provide a suitable abstraction for all classes of applications. There is a need for specially designed architectures in application areas where the general purpose micro-controllers suffer from inefficiencies. This thesis focuses in the design of a processor architecture that provides a suitable design abstraction for a class of periodic, event-driven embedded applications such as sensor-monitoring systems. The design principles of the processor architecture are focused on the target application requirements, which are identified as event-driven nature with concurrent task execution and deterministic timing behavior. Additionally, to reduce the design complexity of applications on this novel architecture, an automation framework has been implemented. This thesis presents the design of the processor architecture and the automation framework explaining the suitability of the designed architecture for the target applications. The energy use of the novel architecture is compared with that of PIC12F675 micro-controller to demonstrate the energy-efficiency of the designed architecture.
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