Title page for ETD etd-07292009-090436

Type of Document Master's Thesis
Author Joshi, Anand Mukund
URN etd-07292009-090436
Title Behavioral delay fault modeling and test generation
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Armstrong, James R. Committee Chair
Cyre, Walling R. Committee Member
Gray, Festus Gail Committee Member
  • Fault-tolerant computing.
Date of Defense 1994-05-05
Availability restricted
As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation.

In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults.

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