Title page for ETD etd-08082012-142823

Type of Document Master's Thesis
Author Jeong, Jeong-O
Author's Email Address jeongo9@vt.edu
URN etd-08082012-142823
Title Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Dietrich, Carl B. Committee Chair
Athanas, Peter M. Committee Member
Reed, Jeffrey Hugh Committee Member
  • Software Defined Radio
  • FPGA
  • ZigBee
  • IEEE 802.15.4
  • USRP N210
Date of Defense 2012-07-30
Availability unrestricted
In this thesis, two different cases of hybrid IEEE 802.15.4 PHY (Physical Layer) implementation

are explored. The first case is an FPGA implementation of IEEE 802.15.4 PHY

on the Xilinx Spartan-3A DSP FPGA of USRP N210. All of the signal processing tasks

are performed on the FPGA, while less complex MAC (Media Access Control) layer tasks

are performed in GNU Radio on the host. The second case is an implementation of a

multi-channel IEEE 802.15.4 receiver. A four-channel channelizer is implemented on the

external Virtex 5 FPGA, while the IEEE 802.15.4 receiver is implemented in GNU Radio

on the host. The first case demonstrates how spare resources in USRP’s FPGA can be

used to implement signal processing task while still interfacing with GNU Radio. The

second case builds a platform on which a combination of GNU Radio and an external

FPGA can be used for signal processing and USRP as an RF source. This thesis lays out

the groundwork for more complex wireless protocols to be implemented on any combination

of USRP’s FPGA, an external FPGA, and GNU Radio.

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