Title page for ETD etd-081299-184716

Type of Document Master's Thesis
Author Narnur, Soumya
Author's Email Address soumya@ee.vt.edu
URN etd-081299-184716
Title Model Development, Synthesis and Validation Using the Modeler's Assistant
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Armstrong, James R. Committee Chair
Gray, Festus Gail Committee Member
Ha, Dong Sam Committee Member
  • Synthesis
  • Validation
  • VHDL Modeling
Date of Defense 1999-08-06
Availability unrestricted
This thesis discusses 'Modeler's Assistant', an

interactive graphics tool which aids in the rapid

development of VHDL models. The tool provides

modeling, test bench generation, simulation,

synthesis and validation features. The

'Process Model graph' which has representations

for the concurrent processes is used as the basis

for Modeler's Assistant. Test generation environment is integrated into the

tool. A range of test bench options are provided

to the user. The tool interfaces to 'Synopsys'

VHDL analyzer, graphics debugger and synthesis

tools. Validation of the behavioral model versus

the synthesized structural model is also discussed.

A detailed programming manual with many examples

is provided for the benefit of the user.

  Filename       Size       Approximate Download Time (Hours:Minutes:Seconds) 
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