Title page for ETD etd-08152003-103345

Type of Document Master's Thesis
Author Gray, David Todd
Author's Email Address dagray3@vt.edu
URN etd-08152003-103345
Title Optimization of the Process for Semiconductor Device Fabrication in the MicrON 636 Whittemore Cleanroom Facility
Degree Master of Science
Department Materials Science and Engineering
Advisory Committee
Advisor Name Title
Hendricks, Robert W. Committee Chair
Farkas, Diana Committee Member
Guido, Louis J. Committee Member
  • Transistor
  • Cleanroom
  • Silicon
  • Labview
  • Semiconductor
Date of Defense 2002-12-20
Availability unrestricted
The main objective of this work is to develop and optimize a process for the fabrication of basic semiconductor devices in silicon using the Modu-lab toolset in the MicrON 636 Whittemore cleanroom facility. This toolset is designed to work with four-inch silicon wafers, in a class 10000 cleanroom. Early work on this process produced functioning devices, with low yield and little to no process control. Three aspects of the process were therefore selected for optimization in this work.

The oxidation of the surface of the silicon wafers could not be made to follow models proposed by and accepted in the literature. By carefully changing the airflow in the oxidation furnace module, the uniformity of the oxide layer and the agreement of the growth with models increases to acceptable levels. Also, the effects of redistribution of dopant species due to growth of the oxide layer and the subsequent thermal processing are examined qualitatively.

Phosphorus diffusion in single-crystal silicon has a complex diffusion mechanism involving charged-vacancies, with concentration-dependent diffusion coefficients. It is therefore a complex mathematical problem to model the diffusion of phosphorus from a solid source within the crystal. An empirical model is proposed that accurately predicts the junction depth and sheet resistance of diffused phosphorus layers within the silicon wafer.

Throughout the course of the process it is necessary to monitor the characteristics of the wafers to assure proper conditions. A semiconductor parameter analyzer has been created for this purpose. Our system uses a Keithley model 2400 source meter, Signatone probe station and four-point probe stage, and a PC to measure DC I-V electrical characteristics of materials and devices. The measurements of sheet resistance, as well as device characterization of resistors, p-n junction diodes, and nMOSFETs provides feedback about the accuracy of processing steps, as well as a pedagogical tool for illustrating semiconductor device physics and operation.

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