Title page for ETD etd-08182011-172058

Type of Document Master's Thesis
Author Iyer, Srikrishna
Author's Email Address skr@vt.edu
URN etd-08182011-172058
Title A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Schaumont, Patrick Robert Committee Chair
Shukla, Sandeep K. Committee Member
Yang, Yaling Committee Member
  • Communication Interface-Abstraction Architecture
  • automatic code-generation
  • TinyOS
  • nesC
  • hardware/software co-design
  • co-processor
  • wireless sensor nodes
  • CPU
  • FPGA
Date of Defense 2011-08-09
Availability unrestricted
Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low power FPGA, the peak computational performance of a sensor node can be improved without significant degradation of the standby power dissipation. In this contribution, we present a methodology and tool to enable hardware/software co-design for sensor node application development. We present the integration of nesC, a sensornet programming language, with GEZEL, an easy-to-use hardware description language. We describe the hardware/software interface at different levels of abstraction: at the level of the design language, at the level of the co-simulator, and in the hardware implementation. We use a layered, uniform approach that is particularly suited to deal with the heterogeneous interfaces typically found on small embedded processors. We illustrate the strengths of our approach by means of a prototype application: the integration of a hardware-accelerated crypto-application in a nesC application.
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