Title page for ETD etd-08182012-001148

Type of Document Dissertation
Author Iskander, Yousef Shafik
URN etd-08182012-001148
Title Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Patterson, Cameron D Committee Chair
Burdisso, Ricardo A. Committee Member
Martin, Thomas L. Committee Member
Plassmann, Paul D. Committee Member
Riad, Sedki Mohamed Committee Member
  • partial reconfiguration
  • reconfigurable computing
  • FPGA
  • development
  • debug
  • design validation
Date of Defense 2012-08-06
Availability unrestricted
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.
  Filename       Size       Approximate Download Time (Hours:Minutes:Seconds) 
 28.8 Modem   56K Modem   ISDN (64 Kb)   ISDN (128 Kb)   Higher-speed Access 
  Iskander_YS_D_2012.pdf 1.98 Mb 00:09:09 00:04:42 00:04:07 00:02:03 00:00:10

Browse All Available ETDs by ( Author | Department )

dla home
etds imagebase journals news ereserve special collections
virgnia tech home contact dla university libraries

If you have questions or technical problems, please Contact DLA.