Title page for ETD etd-08202012-095025

Type of Document Master's Thesis
Author Shagrithaya, Kavya Subraya
URN etd-08202012-095025
Title Enabling Development of OpenCL Applications on FPGA platforms
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Plassmann, Paul E. Committee Member
Schaumont, Patrick Robert Committee Member
  • FPGA
  • AutoESL
  • OpenCL
  • Convey
  • HPC
Date of Defense 2012-08-06
Availability unrestricted
FPGAs can potentially deliver tremendous acceleration in high-performance server and em-

bedded computing applications. Whether used to augment a processor or as a stand-alone

device, these reconfigurable architectures are being deployed in a large number of implemen-

tations owing to the massive amounts of parallelism offered. At the same time, a significant

challenge encountered in their wide-spread acceptance is the laborious efforts required in

programming these devices. The increased development time, level of experience needed by

the developers, lower turns per day and difficulty involved in faster iterations over designs

affect the time-to-market for many solutions. High-level synthesis aims towards increasing

the productivity of FPGAs and bringing them within the reach software developers and

domain experts. OpenCL is a specification introduced for parallel programming purposes

across platforms. Applications written in OpenCL consist of two parts - a host program

for initialization and management, and kernels that define the compute intensive tasks. In

this thesis, a compilation flow to generate customized application-specific hardware descrip-

tions from OpenCL computation kernels is presented. The flow uses Xilinx AutoESL tool to

obtain the design specification for compute cores. An architecture provided integrates the

cores with memory and host interfaces. The host program in the application is compiled and

executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end

flow that provides abstraction of hardware at the front-end.

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