Title page for ETD etd-08252004-140501

Type of Document Master's Thesis
Author Poetter, Alexandra Vanessa
Author's Email Address apoetter@vt.edu
URN etd-08252004-140501
Title JHDLBits: An Open-Source Model for FPGA Design Automation
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Martin, Thomas L. Committee Member
Patterson, Cameron D. Committee Member
  • Hardware Description Language
  • JHDLBits
  • JHDL
  • JBits
  • FPGA
  • Design Automation
Date of Defense 2004-08-23
Availability unrestricted
Today's Field Programmable Gate Array (FPGA) research community could use an extensible tool flow enabling designers to examine new algorithms and new methods of interacting with FPGA configurations. One such flow is JHDLBits, which integrates two prominent FPGA design environments: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a sandbox to explore advanced interactions with FPGA configurations. This thesis presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components -- JHDL, JBits3 for Virtex-II, the ADB connectivity database, and VTsim, a Virtex-II device simulator -- are linked together to provide an integrated design environment. Strategies and philosophies of the open source movement are also examined to successfully establish the support for and involvement of the FPGA research community throughout the JHDLBits open source endeavor.
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