Title page for ETD etd-08302010-025430

Type of Document Master's Thesis
Author Vivekraja, Vignesh
Author's Email Address vigneshv@vt.edu
URN etd-08302010-025430
Title Low-Power, Stable and Secure On-Chip Identifiers Design
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Nazhandali, Leyla Committee Chair
Ha, Dong Sam Committee Member
Schaumont, Patrick Robert Committee Member
  • Hardware Security
  • Low Power
  • Process Variation
  • PUF
Date of Defense 2010-08-27
Availability unrestricted
Trustworthy authentication of an object is of extreme importance for secure protocols. Traditional methods of storing the identity of an object using non-volatile memory is insecure. Novel chip-identifiers called Silicon Physical Unclonable Functions (PUFs) extract the random process characteristics of an Integrated Circuit to establish the identity. Though such types of IC identifiers are difficult to clone and provide a secure, yet an area and power efficient authentication mechanism, they suffer from instability due to variations in environmental conditions and noise. The decreased stability imposes a penalty on the area of the PUF circuit and the corresponding error correcting hardware, when trying to generate error-free bits using a PUF.

In this thesis, we propose techniques to improve the popular delay-based PUF architectures holistically, with a focus on its stability. In the first part, we investigate the effectiveness of circuit-level optimizations of the delay based PUF architectures. We show that PUFs which operate in the subthreshold region, where the transistor supply voltage is maintained below the threshold voltage of CMOS, are inherently more stable than PUFs operating at nominal voltage because of the increased difference in characteristics of transistors at this region. Also, we show that subthreshold PUF enjoys higher energy and area efficiency. In the second part of the thesis, we propose a feedback-based supply voltage control mechanism and a corresponding architecture to improve the stability of delay-based PUFs against variations in temperature.

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