Title page for ETD etd-09082000-03290016

Type of Document Master's Thesis
Author Jagasivamani, Meenatchi
Author's Email Address meenatchi.jagasivamani@intel.com
URN etd-09082000-03290016
Title Development of a Low-Power SRAM Compiler
Degree Master of Engineering
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Ha, Dong Sam Committee Chair
Armstrong, James R. Committee Member
Tront, Joseph G. Committee Member
  • SRAM
  • compiler
  • static
  • generator
  • VLSI
  • memory
  • low-power
  • RAM
Date of Defense 2000-09-01
Availability unrestricted
Considerable attention has been paid to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM.

In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler generates an SRAM layout based on a given SRAM size, input by the user, with the option of choosing between fast vs. low-power SRAM. Array partitioning is used to partition the SRAM into blocks in order to reduce the total power consumption.

Experimental results show that the low-power SRAM is capable of functioning at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20 MHz. In this report, we discuss the implementation of the SRAM compiler from the basic component to the top-level SKILL code functions, as well as simulation results and discussion.

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