Title page for ETD etd-09092003-235330

Type of Document Dissertation
Author Bai, Yuming
URN etd-09092003-235330
Title Optimization of Power MOSFET for High-Frequency Synchronous Buck Converter
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Huang, Alex Q. Committee Chair
Boroyevich, Dushan Committee Member
Ha, Dong Sam Committee Member
Lai, Jih-Sheng Jason Committee Member
Lu, Guo-Quan Committee Member
  • Optimization
  • Buck Converter
  • Trench MOSFET
Date of Defense 2003-08-28
Availability unrestricted
Evolutions in microprocessor technology require the use of a high-frequency synchronous buck converter (SBC) in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency also causes more power loss on MOSFETs. Optimization of the MOSFETs plays an important role in the system performance.

Circuit and device modeling is important in understanding the relationship between the device parameters and the power loss. The gate-to-drain charge (Qgd) is studied by a novel nonlinear model and compared with the simulation results. A new switching model is developed, which takes into account the effect of parasitic inductance on the switching process. Another model for dv/dt-induced false triggering-on relates the false-trigger-on voltage with the parasitic elements of the device and the circuits.

Some techniques are proposed to reduce the simulation time of FEA in the circuit simulation. Based on this approach, extensive simulations are performed to study the switching performance of the MOSFET with the effect of the parasitic elements. Directed by the analytical models and the experience acquired in the circuit simulation, the MOSFET optimization is realized using FEA. Different optimization algorithms are compared. The experimental results show that the optimized MOSFETs surpass the mainstream commercialized products in both cost and performance.

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