Title page for ETD etd-09092010-094913

Type of Document Master's Thesis
Author Raja Gopalan, Sureshwar
Author's Email Address sureshr@vt.edu
URN etd-09092010-094913
Title Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Patterson, Cameron D. Committee Chair
Martin, Thomas L. Committee Member
Plassmann, Paul E. Committee Member
  • FPGAs
  • Reconfigurable Computing
  • Automatic Floorplanning
Date of Defense 2010-09-01
Availability unrestricted
FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address the implementation problem using a divide-and-conquer approach. The PATIS automatic floorplanner enables dynamic modular design, which sacrifices some design speed and area optimization for faster implementation of layout changes, including addition of debug logic. Automatic generation of a timing-driven floorplan for a partially reconfigurable design aims to remove the need for implementation iterations to meet all constraints. Floorplan speculation may anticipate small changes to a design. Although PATIS supports incremental design, complete re-implementation is still rapid because the partial bitstream for each block is generated by independent concurrent invocations of the standard Xilinx tools.

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