Title page for ETD etd-09172004-010535

Type of Document Master's Thesis
Author Fong, Ryan Joseph Lim
URN etd-09172004-010535
Title Improving Field-Programmable Gate Array Scaling Through Wire Emulation
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Co-Chair
Jones, Mark T. Committee Co-Chair
Patterson, Cameron D. Committee Member
  • Xilinx
  • wire
  • FPGA
  • scaling
  • emulation
  • ICAP
  • self-reconfiguration
  • Virtex-II
Date of Defense 2004-09-03
Availability unrestricted
Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag behind ASICs due to interconnection scalability issues. To improve FPGA scalability, this thesis proposes an architectural enhancement to improve global communications in large FPGAs, where chip-length programmable interconnects are slow. It is expected that this architectural enhancement, based on wire emulation techniques, can reduce chip-length communication latency and routing congestion. A prototype wire emulation system that uses FPGA self-reconfiguration as a non-traditional means of intra-FPGA communication is implemented and verified on a Xilinx Virtex-II XC2V1000 FPGA. Wire emulation benefits and impact to FPGA architecture are examined with quantitative and qualitative analysis.
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