Title page for ETD etd-10082012-021855

Type of Document Dissertation
Author Frangieh, Tannous
Author's Email Address tannous@vt.edu
URN etd-10082012-021855
Title A Design Assembly Technique for FPGA Back-End Acceleration
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Dietrich, Carl B. Committee Member
Feng, Wu-Chun Committee Member
Nelson, Brent E. Committee Member
Schaumont, Patrick Robert Committee Member
  • Configurable Computing
  • FPGA Productivity
  • Design Assembly Flow
  • Electronic Design Automation
  • Design Reuse
Date of Defense 2012-09-28
Availability unrestricted
Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.
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