Title page for ETD etd-10102009-020318

Type of Document Master's Thesis
Author Gadagkar, Ashish
URN etd-10102009-020318
Title Timing distribution in VHDL behavioral models
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Armstrong, James R. Committee Chair
Cyre, Walling R. Committee Member
Gray, Festus Gail Committee Member
  • Computer-aided design.
Date of Defense 1992-04-15
Availability restricted

This thesis describes a new CAD tool, TIMESPEC, developed for solving the timing distribution problem of allocating realistic delays to the internal primitives of a digital device. The inconsistencies in the manufacturer's specifications are also detected and corrected. Therefore, TIMESPEC enables the use of imbedded timing in behavioral VHDL models, thereby providing accurate VHDL descriptions. Due to this modeling methodology, the end-to-end delays for all the paths in the digital device are made available. Also, due to the Register Transfer Level (RTL) of abstraction, which is represented by a process model graph, there is close correspondence with the actual device being modeled. Thus a better insight into the timing problems is provided and synthesis is possible from the resulting models.

A linear programming approach is employed for solving the timing distribution problem. An interface is provided with an X-windows based graphical tool, the Modeler's Assistant. This provides a graphical interface for TIMESPEC. An important feature, that is made available by this interface, is the enumeration of all the input-to-output paths in the device. Thus a CAD tool is made available for system or chip designers/modelers for building accurate VHDL models where the timing is incorporated using the imbedded timing method.

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