Type of Document Master's Thesis Author Atiniramit, Prinya Author's Email Address firstname.lastname@example.org URN etd-101299-012534 Title Design and Implementation of an FPGA-based Adaptive filter Single-User Receiver Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Athanas, Peter M. Committee Chair Jones, Mark T. Committee Member Reed, Jeffrey Hugh Committee Member Keywords
- adaptive filter receiver
Date of Defense 1999-09-17 Availability unrestricted AbstractDuring the last decade, the wireless communications industry has grown rapidly. Driven by market demand, service providers are continuously looking for better systems. The main focus of continued research has been to increase the quality of services and system capacity. The Code Division Multiple Access (CDMA) cellular system had been proposed for use as a new standard for cellular telephone systems.
A great deal of research has been conducted to develop receiver structures useful for CDMA systems. Traditional receivers such as the correlation and RAKE receivers are vulnerable to the near-far problem, i.e., the problem encountered when one received signal power is stronger than another. This problem is common in mobile environments.
For single-user receivers, adaptive filtering techniques can be employed to alleviate multiple access interference and the near-far problem. In this thesis, an adaptive filter receiver is implemented on the FPGA-based configurable computing platform called GigaOps G900. By using FPGAs, designers can implement special-purpose signal processing architectures using specialized data paths, optimized sequencing, and pipelining while still providing some flexibility. This results in better overall system performance, resource utilization, and reduced power consumption.
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