Title page for ETD etd-11052005-132203

Type of Document Master's Thesis
Author Agarwal, Deepak
Author's Email Address deepaka@vt.edu
URN etd-11052005-132203
Title An 8 GHz Ultra Wideband Transceiver Testbed
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Ellingson, Steven W. Committee Member
Patterson, Cameron D. Committee Member
  • high-speed datapath
  • software radio
  • FPGA
  • ultra-wideband
Date of Defense 2005-10-07
Availability unrestricted
Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and FPGAs. This thesis presents the digital design for an impulse-based ultra wideband communication system capable of supporting raw data rates of up to 100 MB/s. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non real-time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes. As proof-of-concept, a scaled down prototype receiver which utilized 2 ADCs and a Xilinx Virtex-II Pro (XC2VP30) FPGA was fabricated and tested.
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