Title page for ETD etd-11292010-145142

Type of Document Master's Thesis
Author Subbarayan, Guruprasad
Author's Email Address guruspra@vt.edu
URN etd-11292010-145142
Title Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Patterson, Cameron D. Committee Chair
Hsiao, Michael S. Committee Member
Martin, Thomas L. Committee Member
  • FPGAs
  • Partial Reconfiguration
  • Bus macros
Date of Defense 2010-11-19
Availability restricted
FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed has resulted in longer runtimes of the implementation tools. We address the implementation problem using a divide-and-conquer approach in which some device area and circuit speed is sacrificed for improved implementation turnaround time. The PATIS floorplanner enables dynamic modular design that accelerates implementation for incremental changes to a design. While the existing implementation flows facilitate timing closure late in the design cycle by reusing the layout of unmodified blocks, dynamic modular design accelerates implementation by achieving timing closure for each block independently. A complete re-implementation is still rapid as the design blocks can be processed by independent and concurrent invocations of the standard tools. PATIS creates the floorplan for implementing modules in the design. Bus macros serve as module interfaces and enable independent implementation of the modules. The dynamic modular design flow achieves around 10x speedup over the standard design flow for our benchmark designs.
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