Title page for ETD etd-11302007-113409

Type of Document Master's Thesis
Author Gantz, Kevin Francis
Author's Email Address kgantz@vt.edu
URN etd-11302007-113409
Title Fabrication of Three-Dimensionally Independent Microchannels Using a Single Mask Aimed at On-Chip Microprocessor Cooling
Degree Master of Science
Department Mechanical Engineering
Advisory Committee
Advisor Name Title
Agah, Masoud Committee Chair
Huxtable, Scott T. Committee Member
Nazhandali, Leyla Committee Member
Raman, Sanjay Committee Member
  • nonlinear regression
  • isotropic etching
  • chip cooling
  • CMOS compatible
  • RIE lag
  • microfluidics
Date of Defense 2007-11-28
Availability unrestricted
A novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. This single-mask process reduces risk of damage to the chip and provides the capability to cool high-heat-flux microprocessors for the next 10 years, and for an even longer time once the geometry of the channels is optimized.
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