Title page for ETD etd-12032004-111910

Type of Document Master's Thesis
Author Bhatia, Nikhil S
Author's Email Address nbhatia@vt.edu
URN etd-12032004-111910
Title A Physical Layer Implementation of Reconfigurable Radio
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Jones, Mark T. Committee Member
Reed, Jeffrey Hugh Committee Member
  • System Generator
  • Software Radio
  • FPGA
  • Reconfigurable Radio
Date of Defense 2004-12-03
Availability unrestricted
The next generation of wireless communications will demand the use of software radio technology as the basic architecture to support multi-standard, multi-mode and future-proof radio designs. Software-defined radios are configurable devices in which the physical layer can be reprogrammed to support various standards. Field programmable architectures provide a suitable platform to achieve such run-time reconfigurations of the physical layer of the radio. This thesis explores the use of FPGAs in the design of reconfigurable radios. The results presented here demonstrate how FPGAs can be used to provide the flexibility, performance, efficiency and better resource utilization while meeting the speed and area constraints set by a particular design. The partial reconfiguration feature available in the state-of-the art FPGAs has been exploited to implement the baseband physical layer of reconfigurable radio which can be altered to support various modulations schemes for different wireless standards. The design flow for partial reconfiguration along with the implementation results on two different FPGA platforms is presented. The experiments presented in this thesis make use of System Generator for DSP, a productivity tool from Xilinx, to design and to simulate system-level models in a MATLAB/Simulink environment, and to obtain timing and resource utilization results before implementing the design on actual hardware.
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