Title page for ETD etd-12052001-095443

Type of Document Master's Thesis
Author Shikalgar, Sameer Tajuddin
Author's Email Address sshikalg@vt.edu
URN etd-12052001-095443
Title Reduction of Average Cycle Time at a Wafer Fabrication Facility
Degree Master of Science
Department Industrial and Systems Engineering
Advisory Committee
Advisor Name Title
Sarin, Subhash C. Committee Chair
Koelling, Charles Patrick Committee Member
Teague, Dean Committee Member
  • dispatching
  • scheduling
Date of Defense 2000-08-25
Availability unrestricted
This research is concerned with the development of effective solutions for the reduction of average cycle time at a wafer fabrication facility. The wafer fabrication environment is quite different from the usual flow shop or job shop environments, with a distinguishing feature being the reentrant flow of the lots through the system. Lots at different stages of their manufacturing cycle may revisit the machines. This gives rise to the need of effective policies to sequence lots through the system.

The study is being conducted on a M/A-COM's wafer fabrication system. The facility on which the study is being conducted is based in Roanoke, VA. The facility consists of 92 machines and its products can be classified into six different types. The data required for each product such as routing, processing times, yield at each operation etc. have been acquired from the facility. Two methodologies have been developed to effect a reduction in the cycle time of the products at M/A-COM's facility. The first methodology is heuristic procedure based on the idea of reducing idle time on the bottleneck machine. The second methodology is based on mathematical programming.

For the first methodology, the manufacturing system is simulated using AutoSchedAP, which is part of the AutoSimulations Inc. software package. The software enables the accurate modeling of the existing system using actual part routes, station definitions, operator definitions, shift calendars, input orders, machine breakdowns and processing and setup time distributions. The proposed approach, to reduce cycle time, is based on the principle of reduction of idle time at the bottleneck machine. The bottleneck machine controls the throughput of the system and any unnecessary idle time at the bottleneck leads to an increase in the average cycle time. The AutoSchedAP software enables the user to write custom scheduling rules using C++ and integrate it with the simulation model. The performance of the proposed procedure is compared with those of various other scheduling rules in the software.

The second proposed methodology models the system as an integer program. The integer program reads the various machine and product data and establishes the optimal flow of the lots through the system. The integer program uses the start time of lots, at various operations, as variables and outputs the time at which each lot should be started at each operation. The integer program is solved using CPLEX, which is a linear and integer programming software. Presently, various methods are being analyzed to relax the integer program into an equivalent linear/nonlinear program, since solving an integer program consumes a lot of time, even for small problems.

A third methodology has also been proposed. This methodology concerns the modeling of the system on the basis of a conjunctive-disjunctive graph. The main idea in this methodology is that the minimization of maximum lateness at each operation would result in the minimization of maximum cycle time of the overall system.

Some preliminary results obtained are presented. Also, the work in progress is described.

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