Title page for ETD etd-12202010-144158

Type of Document Master's Thesis
Author Bhardwaj, Prabhaav
Author's Email Address pbjdoe@vt.edu
URN etd-12202010-144158
Title Framework for Hardware Agility on FPGAs
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Plassmann, Paul E. Committee Member
Schaumont, Patrick Robert Committee Member
  • Virtex 5
  • Dynamic Routing
  • FPGA
  • Reconfigurable Computing
Date of Defense 2010-12-15
Availability unrestricted
As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit, General Purpose Processor, and System on Chip are the preferred devices for solving computational problems. Each of these platforms has its own specific advantages and disadvantages, which need to be accounted for during application development. Flexible radio communications has been dominated by Software Defined Radios. However, research in industry and universities has successfully developed run-time reconfiguration tools to make FPGA designs more flexible and thus vastly reducing configuration times. Developers now have a more powerful platform with dense Digital Signal Processor resources and the flexibility of SDR. Xilinx offers tools such as partial reconfiguration, which is a special modification of the standard tool-flow that supports configuration of the selected partial regions on an FPGA. The AgileHW project improves on the Xilinx tools resource allocation and routing scheme to increase the design agility and productivity. This thesis advances the AgileHW reconfigurable platform so developers can use the newer technology to build enhanced designs.
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