Title page for ETD etd-12212009-235313

Type of Document Master's Thesis
Author Nair, Sujit S
Author's Email Address snair83@vt.edu
URN etd-12212009-235313
Title Coarse Radio Signal Classifier on a Hybrid FPGA/DSP/GPP Platform
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Bostian, Charles W. Committee Chair
MacKenzie, Allen B. Committee Member
Patterson, Cameron D Committee Member
  • SDR
  • FPGA
  • DSP
  • GPP
  • Signal Classifier
  • Keywords: Cognitive Radio
Date of Defense 2009-12-07
Availability unrestricted
The Virginia Tech Universal Classifier Synchronizer (UCS) system can enable a cognitive receiver to detect, classify and extract all the parameters needed from a received signal for physical layer demodulation and configure a cognitive radio accordingly. Currently, UCS can process analog amplitude modulation (AM) and frequency modulation (FM) and digital narrow band M-PSK, M-QAM and wideband signal orthogonal frequency division multiplexing (OFDM). A fully developed prototype of UCS system was designed and implemented in our laboratory using GNU radio software platform and Universal Software Radio Peripheral (USRP) radio platform. That system introduces a lot of latency issues because of the limited USB data transfer speeds between the USRP and the host computer. Also, there are inherent latencies and timing uncertainties in the General Purpose Processor (GPP) software itself. Solving the timing and latency problems requires running key parts of the software-defined radio (SDR) code on a Field Programmable Gate Array (FPGA)/Digital Signal Processor (DSP)/GPP based hybrid platform.

Our objective is to port the entire UCS system on the Lyrtech SFF SDR platform which is a hybrid DSP/FPGA/GPP platform. Since the FPGA allows parallel processing on a wideband signal, its computing speed is substantially faster than GPPs and most DSPs, which sequentially process signals. In addition, the Lyrtech Small Form Factor (SFF)-SDR development platform integrates the FPGA and the RF module on one platform; this further reduces the latency in moving signals from RF front end to the computing component. Also for UCS to be commercially viable, we need to port it to a more portable platform which can be transitioned to a handset radio in the future.

This thesis is a proof of concept implementation of the coarse classifier which is the first step of classification. Both fixed point and floating point implementations are developed and no compiler specific libraries or vendor specific libraries are used. This makes transitioning the design to any other hardware like GPPs and DSPs of other vendors possible without having to change the basic framework and design.

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