Title page for ETD etd-12212011-234051

Type of Document Master's Thesis
Author Sukhavasi, Vijay Krishna
URN etd-12212011-234051
Title Steady State Testing and Analysis of a Phasor Measurement Unit
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Centeno, Virgilio A. Committee Chair
Conners, Richard W. Committee Member
De La Ree Lopez, Jaime Committee Member
  • GPS
  • synchronization
  • steady state
  • PMU
  • DUT
Date of Defense 2011-12-13
Availability restricted
Phasor Measurement Units (PMUs) have been instrumental in building a reliable and robust Power System. Recent blackouts have increased the importance of PMUs and PMUs from various manufacturers are being installed in the in large quantities in the North American Grid. The interoperability and accuracy of these PMUs is important to obtain full benefit of the wide area monitoring systems. With the large number of installed PMUs it has become necessary to validate their performance and understand the limitations of each model. A test system was built by NIST in cooperation with NASPI to test for compliance to the existing IEEE C37.118 standard. This thesis presents the development of a Steady State Test System at Virginia Tech based on the NIST Steady State Testing system. The various issues that were faced during the process of development are discussed and the methodology implemented for solving these problems is described. This thesis also presents the additional benefits derived from the results obtained when different PMUs were tested using the Virginia Tech PMU Steady State Test System.
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