Title page for ETD etd-12222010-172018

Type of Document Dissertation
Author Schneider, Scott
Author's Email Address scschnei@cs.vt.edu
URN etd-12222010-172018
Title Shared Memory Abstractions for Heterogeneous Multicore Processors
Degree PhD
Department Computer Science
Advisory Committee
Advisor Name Title
Nikolopoulos, Dimitrios S. Committee Chair
Andrade, Henrique C. M. Committee Member
Back, Godmar V. Committee Member
Cameron, Kirk W. Committee Member
Ribbens, Calvin J. Committee Member
  • Parallel Programming
  • EMM
  • Cell BE
  • Programming Models
  • Parallel Hardware Architecture
Date of Defense 2010-12-10
Availability unrestricted
We are now seeing diminishing returns from classic single-core processor designs, yet the number of transistors available for a processor is still increasing. Processor architects are therefore experimenting with a variety of multicore processor designs. Heterogeneous multicore processors with Explicitly Managed Memory (EMM) hierarchies are one such experimental design which has the potential for high performance, but at the cost of great programmer effort. EMM processors have cores that are divorced from the normal memory hierarchy, thus the onus is on the programmer to manage locality and parallelism. This dissertation presents the Cellgen source-to-source compiler which moves some of this complexity back into the compiler. Cellgen offers a directive-based programming model with semantics similar to OpenMP for the Cell Broadband Engine, a general-purpose processor with EMM. The compiler implicitly handles locality and parallelism, schedules memory transfers for data parallel regions of code, and provides performance predictions which can be leveraged to make scheduling decisions. We compare this approach to using a software cache, to a different programming model which is task based with explicit data transfers, and to programming the Cell directly using the native SDK. We also present a case study which uses the Cellgen compiler in a comparison across multiple kinds of multicore architectures: heterogeneous, homogeneous and radically data-parallel graphics processors.
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