Title page for ETD etd-12232010-123433

Type of Document Master's Thesis
Author Asthana, Rohit Mohan
Author's Email Address rohit.asthana@vt.edu
URN etd-12232010-123433
Title High-Level CSP Model Compiler for FPGAs
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Plassmann, Paul E. Committee Member
Schaumont, Patrick Robert Committee Member
  • High-Level Synthesis
  • FPGAs
  • Models of Computation (MoC)
  • Communicating Sequential Processes (CSP)
  • Autocode Generation
Date of Defense 2010-12-14
Availability unrestricted
The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also enables the designer to try out di erent optimization strategies early in the design stage. In-spite of all these advantages, high-level synthesis design methodologies have not gained much popularity in the mainstream design flow mainly because of the reasons like lack of readability and reliability of the generated register transfer level (RTL) code. The compiler framework presented in this thesis allows the user to draw high-level graphical models of the system. The compiler translates these models into synthesizeable RTL Verilog designs that exhibit their desired functionality following

communicating sequential processes (CSP) model of computation. CSP model of computation introduces a good handshaking mechanism between diff erent components in the design that makes designs less prone to timing violations during implementation and bottlenecks while in actual operation.

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