Title page for ETD etd-522014589642481

Type of Document Dissertation
Author Almajdoub, Salahuddin A.
URN etd-522014589642481
Title A Design Methodology for Physical Design for Testability
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Midkiff, Scott F. Committee Chair
Taylor, Charles Lewis Committee Chair
Armstrong, James R. Committee Member
Davis, Rebecca H. Committee Member
Elshabini-Riad, Aicha A. Committee Member
Sherali, Hanif D. Committee Member
Tront, Joseph G. Committee Member
White, Stephen K. Committee Member
  • Bridging Faults
  • The Labour Party
  • Structure and Agency
  • IDDQ Testing
  • Electoral Performance
  • Physical Design for Testability
Date of Defense 1996-07-01
Availability unrestricted
Physical design for testability (PDFT) is a

strategy to design circuits in a way to avoid or

reduce realistic physical faults. The goal of this

work is to define and establish a speci c

methodology for PDFT. The proposed design

methodology includes techniques to reduce

potential bridging faults in complementary

metal-oxide-semiconductor (CMOS) circuits.

To compare faults, the design process utilizes a

new parameter called the fault index. The fault

index for a particular fault is the probability of

occurrence of the fault divided by the testability

of the fault. Faults with the highest fault indices

are considered the worst faults and are targeted

by the PDFT design process to eliminate them

or reduce their probability of occurrence.

An implementation of the PDFT design process

is constructed using several new tools in

addition to other "off-the-shelf" tools. The first

tool developed in this work is a testability

measure tool for bridging faults. Two other

tools are developed to eliminate or reduce the

probability of occurrence of bridging faults with

high fault indices. The row enhancer targets

faults inside the logic elements of the circuit,

while the channel enhancer targets faults inside

the routing part of the circuit.

To demonstrate the capabilities and test the eff

ectiveness of the PDFT design process, this

work conducts an experiment which includes

designing three CMOS circuits from the

ISCAS 1985 benchmark circuits. Several

layouts are generated for every circuit. Every

layout, except the rst one, utilizes information

from the previous layout to minimize the

probability of occurrence for faults with high

fault indices. Experimental results show that the

PDFT design process successfully achieves two

goals of PDFT, providing layouts with fewer

faults and minimizing the probability of

occurrence of hard-to-test faults. Improvement

in the total fault index was about 40 percent in

some cases, while improvement in total critical

area was about 30 percent in some cases.

However, virtually all the improvements came

from using the row enhancer; the channel

enhancer provided only marginal improvements.

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