Type of Document Dissertation Author Ma, Jing URN etd-01202003-151943 Title Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs Degree PhD Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Athanas, Peter M. Committee Co-Chair Jones, Mark T. Committee Co-Chair Midkiff, Scott F. Committee Member Varadarajan, Srinidhi Committee Member Woerner, Brain D. Committee Member Keywords
- Incremental Design
- Design Tool
Date of Defense 2003-01-13 Availability unrestricted AbstractThis dissertation presents a Field Programmable Gate Array (FPGA) design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as gate counts increase to many millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. Different from other incremental placement algorithms, this tool provides the function not only to handle small modifications; it can also incrementally place a large design from scratch at a rapid rate. Incremental approaches are inherently greedy techniques, but when combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An incremental FPGA design tool has been developed, based on the incremental placement algorithm and its background refiner.
Design applications with logical gate sizes varying from tens of thousands to approximately one million are built to evaluate the execution of the algorithms and the design tool. The results show that this incremental design tool is two orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing much quality. The tool presented places designs at the speed of 700,000 system gates per second. The fast processing speed and user-interactive property make the incremental design tool potentially useful for prototype developing, system debugging and modular testing in million-gate FPGA designs.
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28.8 Modem 56K Modem ISDN (64 Kb) ISDN (128 Kb) Higher-speed Access Bibliography.pdf 127.82 Kb 00:00:35 00:00:18 00:00:15 00:00:07 < 00:00:01 Chapte1&2.pdf 218.75 Kb 00:01:00 00:00:31 00:00:27 00:00:13 00:00:01 Chapter3.pdf 432.79 Kb 00:02:00 00:01:01 00:00:54 00:00:27 00:00:02 Chapter4.pdf 215.65 Kb 00:00:59 00:00:30 00:00:26 00:00:13 00:00:01 Chapter5.pdf 220.90 Kb 00:01:01 00:00:31 00:00:27 00:00:13 00:00:01 Chapter6.pdf 451.65 Kb 00:02:05 00:01:04 00:00:56 00:00:28 00:00:02 Chapter7.pdf 2.22 Mb 00:10:17 00:05:17 00:04:37 00:02:18 00:00:11 Chapter8.pdf 87.77 Kb 00:00:24 00:00:12 00:00:10 00:00:05 < 00:00:01 Tableofcontents.pdf 154.69 Kb 00:00:42 00:00:22 00:00:19 00:00:09 < 00:00:01
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