Title page for ETD etd-04272010-020102
|Type of Document
||Intelligent circuit recognition for VLSI layout verification
||Master of Science
|Tront, Joseph G.
|Cyre, Walling R.
|Midkiff, Scott F.
|Date of Defense
The ability to extract higher level information from a circuit netlist is useful
for VLSI layout verification. An extracted gate level description may be used as
input to a gate level simulator for analysis or alternatively may be used as input to
a rule-based expert system that performs verification checking at a higher level of
abstraction. As a VLSI design evolves it is continually checked for correctness.
This implies that the extraction of higher level information is a recurring activity
and should be performed as efficiently as possible. This paper describes an
alternative method that uses intelligence to quicken the extraction process and
compares this method's performance to a more common method.
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