Type of Document Master's Thesis Author Dickenson, William Wesley URN etd-04292004-124035 Title High Performance Applications for the Single-Chip Message-Passing Parallel Computer Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Baker, James M. Jr. Committee Chair Jones, Mark T. Committee Member Michael S, Hsiao Committee Member Keywords
- Chip Multiprocessors
- Message-Passing Systems
- Parallel Applications
- Parallel Architectures
- Single-Chip Systems
- Thread Level Parallelism
Date of Defense 2004-04-22 Availability unrestricted AbstractComputer architects continue to push the limits of modern microprocessors. By using techniques such as out-of-order execution, branch prediction, and dynamic scheduling, designers have found ways to speed execution. However, growing architectural complexity has led to unsustained development and testing times. Shrinking feature sizes are causing increased wire resistances and signal propagation, thereby limiting a design’s scalability. Indeed, the method of exploiting instruction-level parallelism (ILP) within applications is reaching a point of diminishing returns.
One approach to the aforementioned challenges is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP is a unique, tiled architecture aimed at thread-level parallelism (TLP). Identical cores are replicated across the chip, and global wire traces have been eliminated. The nodes are connected via a 2-D grid network and each contains a local memory bank.
This thesis presents the design and analysis of three high-performance applications for SCMP. The results show that the architecture proves itself as a formidable opponent to several current systems.
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