Type of Document Master's Thesis Author Kotteri, Kishore URN etd-05102004-150752 Title Optimal, Multiplierless Implementations of the Discrete Wavelet Transform for Image Compression Applications Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Bell, Amy E. Committee Chair DaSilva, Luiz A. Committee Member Woerner, Brian D. Committee Member Keywords
- simulated annealing
- field programmable gate array
- canonical signed digit
- perfect reconstruction
Date of Defense 2004-04-27 Availability unrestricted Abstract
The use of the discrete wavelet transform (DWT) for the JPEG2000 image compression standard has sparked interest in the design of fast, efficient hardware implementations of the perfect reconstruction filter bank used for computing the DWT. The accuracy and efficiency with which the filter coefficients are quantized in a multiplierless implementation impacts the image compression and hardware performance of the filter bank. A high precision representation ensures good compression performance, but at the cost of increased hardware resources and processing time. Conversely, lower precision in the filter coefficients results in smaller, faster hardware, but at the cost of poor compression performance. In addition to filter coefficient quantization, the filter bank structure also determines critical hardware properties such as throughput and power consumption.
This thesis first investigates filter coefficient quantization strategies and filter bank structures for the hardware implementation of the biorthogonal 9/7 wavelet filters in a traditional convolution-based filter bank. Two new filter bank properties—“no-distortion-mse” and “deviation-at-dc”—are identified as critical to compression performance, and two new “compensating” filter coefficient quantization methods are developed to minimize degradation of these properties. The results indicate that the best performance is obtained by using a cascade form for the filters with coefficients quantized using the “compensating zeros” technique. The hardware properties of this implementation are then improved by developing a cascade polyphase structure that increases throughput and decreases power consumption.
Next, this thesis investigates implementations of the lifting structure—an orthogonal structure that is more robust to coefficient quantization than the traditional convolution-based filter bank in computing the DWT. Novel, optimal filter coefficient quantization techniques are developed for a rational and an irrational set of lifting coefficients. The results indicate that the best quantized lifting coefficient set is obtained by starting with the rational coefficient set and using a “lumped scaling” and “gain compensation” technique for coefficient quantization.
Finally, the image compression properties and hardware properties of the convolution and lifting based DWT implementations are compared. Although the lifting structure requires fewer computations, the cascaded arrangement of the lifting filters requires significant hardware overhead. Consequently, the results depict that the convolution-based cascade polyphase structure (with “z1-compensated” coefficients) gives the best performance in terms of image compression performance and hardware metrics like throughput, latency and power consumption.
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