Title page for ETD etd-05272008-143141

Type of Document Master's Thesis
Author Ying, Yucheng
Author's Email Address ying@vt.edu
URN etd-05272008-143141
Title Device Selection Criteria --Based on Loss Modeling and Figure of Merit
Degree Master of Engineering
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Lee, Fred C. Committee Chair
Wang, Fei Fred Committee Member
Xu, Ming Committee Member
  • Device Selection
  • Loss Modeling
  • Figure of Merit
Date of Defense 2008-03-28
Availability unrestricted
With the increasing speed of the microprocessor and its rapidly increasing demand for power, determining how to power the microprocessors for our computers becomes an important issue. So far, industry has been struggling to operate the VR/VRM at higher and higher switching frequencies while maintaining acceptable power conversion efficiency. As a consequence, the power switches used in the VR/VRM must be able to work efficiently at a higher switching frequency and with a higher current density.

To evaluate the performance of the MOSFET for this low-output-voltage, high-current and high-switching-frequency application, a prevalent criterion, the Figure-of-Merit (FOM), is being widely adopted for determining the top switch of the buck converter in the VR/VRM. By comparing the FOMs of different devices, the device with the lowest FOM value should have the best performance and lead to the lowest loss for this device in the circuit. Qgd*Rdson is a widely accepted and widely used FOM for power devices. Due to the lack of accuracy of the power loss model, this FOM is no longer suitable for VRM applications. Furthermore, the question of how to use this FOM to select the right device for different application is another important issue.

This work presents an investigation of a new Figure-of-Merit based on a more accurate loss model, which includes the factor of Qgs2, the gate-driving voltage and the packaging parasitics. Furthermore, a simple method is proposed to select the right device and gate-driving voltage for different circuit conditions. A new simple and accurate closeform model for device loss with packing parasitics is derived. This model can provide more physical information for each of the device parameters. The loss influence of the different packaging method is analyzed and discussed at the end of the work.

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