Title page for ETD etd-06052012-180711

Type of Document Master's Thesis
Author Zuo, Yongbo
Author's Email Address zyongbo@vt.edu
URN etd-06052012-180711
Title Fair Comparison of ASIC Performance for SHA-3 Finalists
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Nazhandali, Leyla Committee Chair
Schaumont, Patrick Robert Committee Member
Shukla, Sandeep K. Committee Member
  • SHA
  • NIST
  • ASIC
  • Finalist
  • Hardware
  • Encryption
  • Hash
  • Cipher
  • Key
Date of Defense 2012-05-31
Availability unrestricted
In the last few decades, secure algorithms have played an irreplaceable role in the protection of private information, such as applications of AES on modems, as well as online bank transactions. The increasing application of secure algorithms on hardware has made implementations on ASIC benchmarks extremely important. Although all kinds of secure algorithms have been implemented into various devices, the effects from different constraints on ASIC implementation performance have never been explored before.

In order to analyze the effects from different constraints for secure algorithms, SHA-3 finalists, which includes Blake, Groestl, Keccak, JH, and Skein, have been chosen as the ones to be implemented for experiments in this thesis.

This thesis has first explored the effects of different synthesis constraints on ASIC performance, such as the analysis of performance when it is constrained for frequency, or maximum area, etc. After that, the effects of choosing various standard libraries were tested, for instance, the performance of UMC 130nm and IBM 130nm standard libraries have been compared. Additionally, the effects of different technologies have been analyzed, such as 65nm, 90nm, 130nm and 180nm of UMC libraries. Finally, in order to further understand the effects, experiments for post-layout analysis has been explored. While some algorithms remain unaffected by floor plan shapes, others have shown preference for a specific shape, such as JH, which shows a 12% increase in throughput/area with a 1:2 rectangle compared to a square.

Throughout this thesis, the effects of different ASIC implementation factors have been comprehensively explored, as well as the details of the methodology, metrics, and the framework of the experiments. Finally, detailed experiment results and analysis will be discussed in the following chapters.

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