Type of Document Master's Thesis Author Gold, Brian Author's Email Address firstname.lastname@example.org URN etd-07242003-134147 Title Balancing Performance, Area, and Power in an On-Chip Network Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Baker, James M. Jr. Committee Chair Jones, Mark T. Committee Member Michael S, Hsiao Committee Member Keywords
- virtual channels
- crossbar switch
- single chip computer
- message passing
- system on chip
Date of Defense 2003-07-23 Availability unrestricted AbstractSeveral trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications.
The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects.
This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption.
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